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<title>Sample Waveforms for Fifo16Cis.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file Fifo16Cis.v </CENTER></h2>
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design Fifo16Cis.v. The design Fifo16Cis.v has a depth of 8 words of 16 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=Fifo16Cis_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
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